// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:13 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  pcs_raw_sram_bootloader.v
//
//  Raw PCS SRAM bootloader
//
//  Original Author: Dom Spagnuolo
//  Current Owner:   Dom Spagnuolo
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: spagnuol $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/pcs_raw_sram_bootloader.v $
//    $DateTime: 2015/12/22 06:27:08 $
//    $Revision: #5 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"
`include "dwc_e12mp_phy_x4_ns_cr_macros.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_pcs_raw_sram_bootloader (
// Clocks and resets
input  wire                       cr_clk,
input  wire                       cr_rst,
// Control inputs
input  wire                       sram_bypass,
input  wire                       sram_init_done_in,
input  wire [11:0]                prgm_size,
// Control outputs
output wire                       sram_init_done_out,
// ROM interface
output reg                        cr_mem_rd_en,
output reg  [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_mem_addr,
input wire  [`DWC_E12MP_X4NS_CR_DATA_RANGE] cr_mem_rd_data,
// SRAM interface
output reg                        sram_wr_en,
output reg  [`DWC_E12MP_X4NS_SRAM_ADDR_RANGE] sram_addr,
output wire [`DWC_E12MP_X4NS_CR_DATA_RANGE] sram_wr_data
);

// ------------------------
// Nets declarations
// ------------------------
wire [`DWC_E12MP_X4NS_CR_ADDR_RANGE] prgm_end = {`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM0,prgm_size[11:0]};
reg                        cr_mem_rd_done;
reg                        sram_init_done_int;

// Process to read data from ROM
always @(posedge cr_clk or posedge cr_rst) begin
   if (cr_rst) begin
      cr_mem_rd_done    <= 1'b0;
      cr_mem_rd_en      <= 1'b0;
      cr_mem_addr       <= {`DWC_E12MP_X4NS_CR_TYPE_RAW_PCS_ROM0,12'd0};
   end else begin
      // Generate rd_en signal out of reset
      if (!sram_bypass & !sram_init_done_in & (cr_mem_addr < prgm_end) ) begin
         cr_mem_rd_en   <= 1'b1;
      end else begin
         cr_mem_rd_done <= 1'b1;
         cr_mem_rd_en   <= 1'b0;
      end
      // Increment address to ROM when cr_mem_rd_en is asserted
      if (cr_mem_rd_en) begin
         cr_mem_addr    <= cr_mem_addr + 1'd1;
      end
   end
end

// Process to write_data to SRAM
always @(posedge cr_clk or posedge cr_rst) begin
   if (cr_rst) begin
      sram_init_done_int <= 1'b0;
      sram_wr_en         <= 1'b0;
      sram_addr          <= {`DWC_E12MP_X4NS_CR_DATA_LEN{1'b0}};
   end else begin
      // Increment address to SRAM when sram_wr_en is asserted
      if (sram_wr_en) begin
         sram_addr       <= sram_addr + 1'd1;
      end
      // Generate wr_en signal to SRAM 1 cycle after rd_en to ROM
      sram_wr_en         <= cr_mem_rd_en;
      sram_init_done_int <= cr_mem_rd_done;
   end
end

// Pass through the data read from the ROM to the SRAM
assign sram_wr_data = cr_mem_rd_data;

// Generate the sram_init_done_out signal
assign sram_init_done_out = sram_init_done_in | sram_init_done_int;

endmodule
